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NCMOS NMaximum Output Current : 100mA(VOUT=5.0V) GBattery use NHighly Accurate Output Voltage : 2% NOutput Voltage Range : 2.0V~ 6.0V NHighly Accurate Voltage Detection : 2% NNo Load Supply Current : 3.2A(5.0V) NSOT-25 Package
GBattery life & charge detection GMemory battery back-up circuits GMicroprocessor reset circuitry GPower failure detection GVoltage Sources Reference GCameras, Video Cameras GVarious Portable Devices
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The XC66D series consists of a voltage detector and voltage regulator built into the one chip and is, essentially, a voltage regulator with voltage detect capabilities. Low power consumption and high accuracy is achieved through CMOS and laser trimming technologies. The detector features an output driver, hysteresis circuit, comparator and extremely accurate standard voltage. The regulator features an error amplification circuit, output driver with current limiter functions, minimal input-output voltage differential and similary accurate standard voltage. SOT-25 (150mW) package is available.
Maximum Output Current
: 100mA (Within max. continuous total power dissipation, VOUT=5.0V) Output Voltage Range : 2.0V ~ 6.0V (0.1V steps, Standard 5.0V) Highly Accurate Output Voltage : Fixed voltage accuracy 2% Output Voltage Temperature Characteristics : Typ. 100ppm/C Detect Voltage Range : 1.8V ~ 6.0V (0.1V steps) Highly Accurate Detect Voltage : Fixed voltage accuracy 2% Low Power Consumption : Typ. 3.2A (VOUT= 5.0V)
Detect Voltage Temperature Characteristics : Typ. 100ppm/C Detect Voltage Output Configuration : N-ch open drain CMOS (High level =VOUT) Input Stability : Typ. 0.1%/V Ultra Small Packages : SOT- 25 (150mW) mini-mold

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PIN NUMBER 1 2 3 4 5
PIN NAME VDOUT VSS VDIN VIN VOUT
FUNCTION Voltage Detect Output Ground Voltage Detect Input Power Supply Voltage Regulator Output
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GOrdering Information
DESIGNATOR a
DESCRIPTION Detector Output Configuration C=CMOS(High level=VOUT) N=N-ch open drain Detect Voltage (VDF) 25=2.5V 38=3.8V
DESIGNATOR d
DESCRIPTION Package Type M=SOT-25
b
e c Regulator Output Voltage (VOUT) 33=3.3V 50=5.0V
Device Orientation R=Embossed Tape (Standard Feed) L=Embossed Tape (Reverse Feed)
GSOT-25
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q
qwer
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w
e
r
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(1) XC66DC CMOS output (High level =VOUT)
(2) XC66DN N-ch open drain
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Ta=25C
PARAMETER Regulator Input Voltage Regulator Output Current Regulator Output Voltage Detector Input Voltage Detector Output Current Detector Output Voltage N-ch open drain output
SYMBOL VIN IOUT VOUT VDIN IDOUT VDOUT
RATINGS VSS -0.3 ~ 12 150 VSS -0.3 ~ VIN +0.3 VSS -0.3 ~ 12 50 VSS -0.3 ~ 12
UNITS V mA V V mA V
CMOS output (High level =VOUT) Pd Topr Tstg
VSS -0.3 ~ VIN +0.3 150 -30 ~ +80 -40 ~ +125 mW C C
Continuous Total Power Dissipation Operating Ambient Temperature Storage Temperature
Note: Please ensure that {(VIN -VOUT ) x IOUT} + {IDOUT x VDOUT} + {VIN x ISS} does not exceed the stated Pd values.
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VDF =1.8V ~ 6.0V, VOUT(T) (Note1) =5V
PARAMETER
Ta=25C
SYMBOL VDF VHYS VIN N-ch
CONDITIONS VIN = VDIN VIN = VDIN
MIN (VDF) x 0.98 (VDF) x 0.02 1.5
TYP VDF (VDF) x 0.05 -
MAX (VDF) x 1.02 (VDF) x 0.08 10.0
UNITS CIRCUIT V V V 1 1 -
Detect Voltage Hysteresis Range Operating Voltage
DETECTOR
Output Current
IDOUT P-ch
VDS=0.5V VSS=1.5V =2.0V =3.0V =4.0V =5.0V VDS=0.9V VIN=VDIN=VOUT=8V (CMOS) VDIN=10V
0.3 3.0 5.0 6.0 7.0 4.9 100 -
2.2 7.7 10.1 11.5 10.3 -5
0.4 100 5 20 260 0.1 100 3.2
-2
1.0 5.1 80 520 0.3 10.0 8.6
2 mA
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A ppm/C V mA mV mV %/V ppm/C V mA 3 1 4 4 4 4 4 4 5
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VDIN Input Current
Detect Voltage Temp. Characteristics
IDIN
VOUT Topr * VDF
-30C Topr 80C
Output Voltage Maximum Output Current Load Stability
REGULATOR
VOUT (E) (Note2) IOUTmax VOUT Vdif (Note3)
VOUT VIN * VOUT
VOUT Topr * VOUT
IOUT=10mA VIN = VOUT(T) + 1V VIN= VOUT(T) + 1V VOUT(E) VOUT(T) x0.9 VIN= VOUT(T) + 1V 1mA IOUT 80mA IOUT =60mA IOUT=10mA VOUT(T) + 1V VIN 10V IOUT =10mA -30C Topr 80C
Input - Output Voltage Differential Input Stability Output Voltage Temp. Characteristics Input Voltage Supply Current
VIN ISS VIN = VOUT(T) +1V
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Note: 1. VOUT(T) : User specified output voltage. 2. VOUT(E) : Effective output voltage. (i.e. the output voltage when a stable (VOUT(T) + 1.0V) is provided, while maintaining a certain IOUT value.) 3. Vdif : Vdif = {VIN1 - VOUT1} VOUT1 : The voltage equal to 98% of the output voltage whenever a stable (VOUT(T) +1.0V) is provided at IOUT. VIN1 : The input voltage when the output is equal to VOUT(E) x 98%.
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GNotes on Use
1. In cases where there is no capacitance (CL), or the capacitance is small, or where a capacitor with an extremely low ESR value is used (e.g. ceramic), please use a capacitor (CL = 1.0F [Tantalum]) in order to stop oscillation that may occur as the phase margin becomes smaller. 2. To reduce impedance between the power supply and the IC's input pin, which in turn will stop oscillation resulting from input voltage changes, connect a capacitor (CIN = more than 1.0F, ESR low) to the input side of the IC. Further, operation may become unstable and oscillation may occur shoud impedance up to the IC's input be high (a state which could be brought about by several factors including which devices are added to the input side, the surrounding wiring and/or the input power supply.) Stability can be improved by regulating increases in input capacitance and by reducing impedance. 3. The regulator's input pin (VIN) and power supply pin are the same. Also, the voltage detector's power supply and the voltage regulator's power supply are the same. Therefore, to have the voltage detector operating normally, it is necessary to apply a voltage larger than the minimum operating voltage (1.5V) to the power supply input pin (VIN). 4. With CMOS output, the detector's output voltage equals the regulator's output voltage following release. Possible changes in the regulator's output voltage (VROUT), following regulator load changes, will be output at the detector's output pin (VDOUT). 5. As the operations of the detector will momentarily respond when steep rise and fall time voltages are input at the power supply pin (VIN), please ensure that the VIN(VDIN) pin's input frequency's rise and fall time is more than 5 sec/V. 6. When using with the detector input pin (VDIN) connected to the regulator output pin (VOUT), the detector will momentarily respond as a result of transient output voltage changes brought about by the regulator's load changes. With large load currents and/or large load transitions from 1mA to 80mA for example, output voltage will momentarily drop, so please add a capacitor where CL=more than 4.7mF.
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GTiming Chart (N-ch open drain pull up voltage =Input voltage VIN)
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GOperational Notes [Detector : CMOS Output ('High' level = VOUT)]
Timing Chart A (VIN=VDIN) 1. When a voltage greater than the release voltage (VDR) is applied to the voltage input pin (VIN, VDIN), input voltage (VIN, VDIN) will gradually fall. When a voltage greater than the detect voltage (VDF) is applied to the voltage input pin (VIN, VDIN), the output pin(VDOUT) voltage will be equal to the regulator's output voltage (VOUT). * With N-ch open drain configurations a state of high impedance means that should the pin be pulled up, voltage will be equal to pull up voltage. 2. When input voltage (VIN, VDIN) fall below detect voltage (VDF), output voltage (VDOUT) will be equal to ground level (VSS). 3. Should input voltage (VIN, VDIN) fall below the minimum operational voltage (VMIN), output will become unstable. Should VDIN fall below VMIN, voltage at the output pin (VDOUT) will be equal to ground level (VSS) . *With N-ch open drain configurations output will equal pull up voltage as the output pin is generally pulled up. 4. Should input voltage (VIN, VDIN) rise above ground voltage (VSS), output voltage (VDOUT) will equal ground level until the release voltage level (VDR) is reached. 5. The output pin voltage (VDOUT) will be equal to the regulator output voltage (VOUT) when input voltage (VIN, VDIN) rises above release voltage. *With N-ch open drain configurations it will be equal to the voltage dependent on pull up. Timing Chart B (VIN=voltages above set-up voltage + input/output voltage differential, VDIN = sweep voltage) Because a voltage higher than the minimum operating voltage is applied to the voltage input pin (VIN), ground voltage will be output at the output pin (VDOUT) during stage 3. (Stages 1, 2, 4, 5 are the same as in A above). Note : The difference between release voltage (VDR) and detect voltage (VDF) is the Hysteresis Range (6).
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Circuit 1
Circuit 2
3
Circuit 3 Circuit 4
Circuit 5
Circuit 6
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(9) REGULATOR OUTPUT VOLTAGE vs. REGULATOR INPUT VOLTAGE

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(10) INPUT/OUTPUT VOLTAGE DIFFERENTIAL vs. REGULATOR OUTPUT CURRENT (11) REGULATOR OUTPUT VOLTAGE vs. AMBIENT TEMPERATURE

(12) INPUT TRANSIENT RESPONSE 1
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(13) INPUT TRANSIENT RESPONSE 2

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(14) LOAD TRANSIENT RESPONSE (15) RIPPLE REJECTION RATE
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